Interrupt handler - Revision history

Aoineko: /* Custom ISR */

2026-01-05T18:00:52Z

‎Custom ISR

2026-01-05T18:00:31Z

‎Custom ISR

2026-01-05T18:00:14Z

‎Custom ISR

2025-10-17T21:06:15Z

‎Resources

2025-10-17T20:07:44Z

2025-10-17T19:38:16Z

2025-10-17T19:36:50Z

‎Hook

2025-10-17T17:48:41Z

2025-10-17T11:59:39Z

2025-10-17T11:50:43Z

@@ Line 41: / Line 41: @@
 When using "<tt>ROM_48K_ISR</tt>", "<tt>ROM_64K_ISR</tt>", NEO mapper targets, or any ROM with <tt>InstallRAMISR</tt> project parameter set to "<tt>RAM0_ISR</tt>" or "<tt>RAM0_SEGMENT</tt>", the MSXgl boot program will switch memory page 0 to point to a ROM segment or RAM where an custom ISR is located.
-This custom ISR is optimized for game and only respond to needed signal: V-blank, H-blank (for MSX2 and above) and Command end (V9990).
+This custom ISR is optimized for game and only respond to the needed signals: V-blank, H-blank (for MSX2 and above) and Command end (V9990).
 == Notes ==

@@ Line 41: / Line 41: @@
 When using "<tt>ROM_48K_ISR</tt>", "<tt>ROM_64K_ISR</tt>", NEO mapper targets, or any ROM with <tt>InstallRAMISR</tt> project parameter set to "<tt>RAM0_ISR</tt>" or "<tt>RAM0_SEGMENT</tt>", the MSXgl boot program will switch memory page 0 to point to a ROM segment or RAM where an custom ISR is located.
-This custom ISR is optimized for game and only respond to needed signal: V-blank, H-blank (for MSX2 and above) and Command termination (V9990).
+This custom ISR is optimized for game and only respond to needed signal: V-blank, H-blank (for MSX2 and above) and Command end (V9990).
 == Notes ==

@@ Line 39: / Line 39: @@
 === Custom ISR ===
-When using "ROM_48K_ISR", "ROM_64K_ISR", NEO mapper targets, or any ROM with InstallRAMISR equal to "RAM0_ISR" or "RAM0_SEGMENT", the MSXgl boot program will switch memory page 0 to point to a ROM segment or RAM where an custom ISR is located.
+When using "<tt>ROM_48K_ISR</tt>", "<tt>ROM_64K_ISR</tt>", NEO mapper targets, or any ROM with <tt>InstallRAMISR</tt> project parameter set to "<tt>RAM0_ISR</tt>" or "<tt>RAM0_SEGMENT</tt>", the MSXgl boot program will switch memory page 0 to point to a ROM segment or RAM where an custom ISR is located.
-This ISR is optimized for game and only respond
+This custom ISR is optimized for game and only respond to needed signal: V-blank, H-blank (for MSX2 and above) and Command termination (V9990).
 == Notes ==

← Older revision		Revision as of 21:06, 17 October 2025
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	== Resources ==		== Resources ==
−	* [https://map.grauw.nl/articles/interrupts.php Interrupts ~~article~~ on the MSX Assembly Page].	+	* ''[https://map.grauw.nl/articles/interrupts.php Interrupts]'' on the MSX Assembly Page.

← Older revision		Revision as of 20:07, 17 October 2025
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	== Notes ==		== Notes ==
	* <sup>#1</sup> In the default interrupt mode (IM 1). The Z80 has two other interrupt modes (IM 0 and IM 2) but only IM 1 is used usually.		* <sup>#1</sup> In the default interrupt mode (IM 1). The Z80 has two other interrupt modes (IM 0 and IM 2) but only IM 1 is used usually.
		+
		+	== Resources ==
		+	* [https://map.grauw.nl/articles/interrupts.php Interrupts article on the MSX Assembly Page].

@@ Line 34: / Line 34: @@
 For the main program to be acknowledged when an interrupt occurs, the BIOS provides hooks in memory that are called in given circumstances. The main program can redirect those hooks to its own function to handle interrupts on its own.
-More interesting hooks:
+Interrupt related hooks:
 * <tt>H.KEYI</tt>: called when any interrupt occurs.
 * <tt>H.TIMI</tt>: called when v-blank interrupt occurs.

@@ Line 12: / Line 12: @@
 Those with knowledge of assembly language should be concerned that the code executed during the interrupt may modify the CPU registers and that when the Z80 returns control to the main program, it will no longer function correctly. Well, you are right to be concerned because there is no automatic mechanism to prevent this!
-As a result, before modifying the value of a register, ISRs save its value in the stack so that it can be restored before returning control to the main program.
+As a result, before modifying the value of any register, ISRs have to save its value in the stack so that it can be restored before returning control to the main program.
 === BIOS ===
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 The video processor sends an interrupt signal at constant intervals after displaying each frame (at 50 or 60 Hz depending on the region) and the BIOS’s ISR uses this interrupt to update some of its variables (frame counter, joystick or keyboard input state…).
 === Custom ISR ===
 == Notes ==
-* <sup>#1</sup> In the default interrupt mode (IM 1)
+* <sup>#1</sup> In the default interrupt mode (IM 1). The Z80 has two other  interrupt modes (IM 0 and IM 2) but only IM 1 is used usually.

@@ Line 9: / Line 9: @@
 The code that is called during an interrupt is called an ISR (interrupt service routine).
 === BIOS ===
-As by default, the main-ROM slot is selected on page 0, a piece of code provided by the BIOS is executed at address <tt>0x0038</tt> each time an interrupt occurs.
+As by default, the main-ROM slot is selected on page 0, it is a piece of code provided by the BIOS that is executed at address <tt>0x0038</tt> each time an interrupt occurs.
 === Custom ISR ===