Z80 wait instructions - Revision history

Aoineko at 10:30, 12 June 2025

2025-06-12T10:30:26Z

Aoineko at 10:28, 12 June 2025

2025-06-12T10:28:57Z

Aoineko at 18:08, 6 April 2024

2024-04-06T18:08:27Z

Aoineko at 18:07, 6 April 2024

2024-04-06T18:07:22Z

Aoineko at 11:48, 3 March 2024

2024-03-03T11:48:52Z

Aoineko at 11:47, 3 March 2024

2024-03-03T11:47:55Z

Aoineko at 11:43, 3 March 2024

2024-03-03T11:43:31Z

Aoineko at 11:24, 3 March 2024

2024-03-03T11:24:09Z

Aoineko at 11:12, 3 March 2024

2024-03-03T11:12:43Z

Aoineko at 11:10, 3 March 2024

2024-03-03T11:10:31Z

@@ Line 1: / Line 1: @@
 Sometimes, the CPU needs to wait a little while without doing anything (for example, when waiting for a device to be ready to communicate).
-It's not an ideal design (we always prefer the CPU to be busy, especially on an 8-bit machine), but it's sometimes the most efficient solution.
+It's not an ideal design (we always prefer the CPU to be busy, especially on an 8-bit machine), but paradoxically, it's sometimes the most efficient solution.
 In this case, we use Z80 assembly instructions that do not modify registers (or as little as possible) so that we don't need to re-establish a context after waiting.

@@ Line 1: / Line 1: @@
-Z80 instruction set that don't change registers value (except for F register):
+Sometimes, the CPU needs to wait a little while without doing anything (for example, when waiting for a device to be ready to communicate).
 {| class="wikitable"
 ! Inst. !! T-S !! Bytes !! Flag modification

@@ Line 39: / Line 39: @@
 | <tt>NOP<br/>NOP<br/>NOP<br/>NOP<br/>NOP</tt> || 25 || 5 || None
 |-
-| <tt>NOP<br/>CP (IY+0)</tt>      || 26 || 4 || C, S, and Z flags modified by definition. P/V detects overflow.
+| <tt>JR $+2<br/>JR $+2</tt>      || 26 || 4 || None
 |-
 | <tt>NOP<br/>CP (HL)<br/>BIT 0,(HL)</tt> || 27 || 4 || C, S, and Z flags modified by definition. P/V detects overflow.<br/>Opposite of the bit #0 is written into the Z flag. C is preserved, N is reset, H is set, and S and P/V are undefined.

@@ Line 21: / Line 21: @@
 | <tt>SCF<br/>RET NC<br/>RET NC</tt> || 17 || 3 || Carry flag set, H and N cleared, rest are preserved.
 |-
-| <tt>NOP<br/>NOP<br/>CP (HL)</tt>|| 18 || 3 || C, S, and Z flags modified by definition. P/V detects overflow.
+| <tt>NOP<br/>JR $+2</tt>         || 18 || 3 || None
 |-
 | <tt>NOP<br/>BIT 0,(HL)</tt>     || 19 || 3 || Opposite of the bit #0 is written into the Z flag. C is preserved, N is reset, H is set, and S and P/V are undefined.

@@ Line 13: / Line 13: @@
 | <tt>JR $+2</tt>                 || 13 || 2 || None
 |-
-| <tt>INC HL<br/>DEC HL</tt>      || 14 || 2 || None
+| <tt>BIT 0,(HL)</tt>             || 14 || 2 || Opposite of the bit #0 is written into the Z flag. C is preserved, N is reset, H is set, and S and P/V are undefined.
 |-
 | <tt>NOP<br/>NOP<br/>NOP</tt>    || 15 || 3 || None

@@ Line 8: / Line 8: @@
 |-
 | <tt>NOP<br/>NOP</tt>            || 10 || 2 || None
-|- style="background-color:lightgray;"
+|-
-| <tt>LD R,A</tt>                 || 11 || 2 || C is preserved, H and N are reset, and alters Z and S. P/V is set if interrupts are enabled, reset otherwise.
+| <tt>SCF<br/>RET NC</tt>         || 11 || 2 || Carry flag set, H and N cleared, rest are preserved.
 |-
 | <tt>JR $+2</tt>                 || 13 || 2 || None
@@ Line 18: / Line 18: @@
 |-
 | <tt>CP (HL)<BR/>CP (HL)</tt>    || 16 || 2 || C, S, and Z flags modified by definition. P/V detects overflow.
 |-
 | <tt>NOP<br/>NOP<br/>CP (HL)</tt>|| 18 || 3 || C, S, and Z flags modified by definition. P/V detects overflow.

@@ Line 33: / Line 33: @@
 | <tt>CP (HL)<BR/>CP (HL)<BR/>CP (HL)</tt> || 24 || 3 || C, S, and Z flags modified by definition. P/V detects overflow.
 |- style="background-color:lightgray;"
-| <tt>INC (HL)<br/>DEC (HL)</tt>  || 24 || 2 || Preserves C flag, N flag is reset, P/V detects overflow and rest are modified by definition.<br/>C flag preserved, P/V detects overflow and rest modified by definition.
+| <tt>INC (HL)<br/>DEC (HL)</tt>  || 24 || 2 || Preserves C flag, N flag is reset, P/V detects overflow and rest are modified by definition.<br/>C flag preserved, P/V detects overflow and rest modified by definition.<br/>⚠️ Not interrupt safe
 |-
 | <tt>NOP<br/>NOP<br/>NOP<br/>NOP<br/>NOP</tt> || 25 || 5 || None
@@ Line 45: / Line 45: @@
 | <tt>CP (IY+0)<br/>CP (HL)</tt>  || 29 || 4 || C, S, and Z flags modified by definition. P/V detects overflow.
 |- style="background-color:lightgray;"
-| <tt>NOP<br/>INC (HL)<br/>DEC (HL)</tt>  || 29 || 3 || Preserves C flag, N flag is reset, P/V detects overflow and rest are modified by definition.<br/>C flag preserved, P/V detects overflow and rest modified by definition.
+| <tt>NOP<br/>INC (HL)<br/>DEC (HL)</tt>  || 29 || 3 || Preserves C flag, N flag is reset, P/V detects overflow and rest are modified by definition.<br/>C flag preserved, P/V detects overflow and rest modified by definition.<br/>⚠️ Not interrupt safe
 |-
 | <tt>BIT 0,(HL)<br/>CP (HL)<br/>CP (HL)</tt> || 30 || 4 || Opposite of the bit #0 is written into the Z flag. C is preserved, N is reset, H is set, and S and P/V are undefined.<br/>C, S, and Z flags modified by definition. P/V detects overflow.
 |}